UVVM - Universal VHDL Verification Methodology - is an Open Source VHDL testbench infrastructure, Architecture, Library and Methodology for making better VHDL testbenches.

UVVM is used to speed up verification and improve the overall FPGA design quality. Applicable for both FPGAs and ASICs, UVVM is used by 20% of VHDL developers worldwide, and it's supported by the European Space Agency (ESA).

You can download the complete UVVM and find all the required documentation on GitHub and UVVM.org.

We also arrange open and on-site courses all over the world on request.

UVVM Utility Library

UVVM Utility Library is a testbench infrastructure library and methodology for verifying FPGAs. This library provides fundamental support for logging, alert handling and result checking. Applying UVVM Utility Library results in a faster testbench development and efficient debug support.

UVVM VVC Framework

UVVM VVC Framework provides a FPGA verification environment with better overview, readability and maintainability. It also increases the probability of detecting corner case design bugs. The tool supports constrained random stimuli, coverage verification and efficient verification reuse.

Vil du vite mer? Ta kontakt

Lars Guntveit
Avdelingsleder, Asker

William Braathen
Leder forretningsutvikling


  • Open Source library
  • Testbench kickstart
  • Great overview and readability
  • Efficient and easy to maintain
  • Modular, reusable and extendable
  • Vital for FPGA development quality
  • Allows simple control of Constr.Rand. and Func.Cov.
  • Seamless integration with OSVVM Constr.Rand and Func.Cov
  • Modern verification methodology