Development tools

To improve the quality and reduce the development time of embedded software, Inventas, formerly Bitivis, is continuously developing our own tools and IP.

Our tools and IP allows Inventas to perform a much better service for our customers, and they also make it possible for our customers to improve their own development projects.

UVVM - Universal VHDL Verification Methodology

UVVM is our VHDL testbench infrastructure, architecture, library and methodology for verifying FPGAs.

More on UVVM below

Register Wizard

The Register Wizard is our tool to accelerate and optimise the design flow for handling register interfaces between software and hardware.

More on Register Wizard below

UVVM - Universal VHDL Verification Methodology

UVVM is an Open Source VHDL testbench infrastructure, Architecture, Library and Methodology for making better VHDL testbenches. UVVM is used to speed up verification and improve the overall FPGA design quality. Applicable for both FPGAs and ASICs. UVVM is used by 20% of VHDL developers worldwide, and it's supported by the European Space Agency (ESA).

You can download the complete UVVM and find all the required documentation on GitHub and

We also arrange open and on-site courses all over the world on request.

UVVM Utility Library

UVVM Utility Library is a testbench infrastructure library and methodology for verifying FPGAs. This library provides fundamental support for logging, alert handling and result checking. Applying UVVM Utility Library results in a faster testbench development and efficient debug support.

UVVM VVC Framework

UVVM VVC Framework provides a FPGA verification environment with better overview, readability and maintainability. It also increases the probability of detecting corner case design bugs. The tool supports constrained random stimuli, coverage verification and efficient verification reuse.


  • Open Source library
  • Testbench kickstart
  • Great overview and readability
  • Efficient and easy to maintain
  • Modular, reusable and extendable
  • Vital for FPGA development quality
  • Allows simple control of Constr.Rand. and Func.Cov.
  • Seamless integration with OSVVM Constr.Rand and Func.Cov
  • Modern verification methodology

Register Wizard

Simple - but powerful. Speed up your design flow. Describe all your registers in a common source file and let the tool generate the code.

Have you ever caught yourself doing one of those annoying copy-paste mistakes where you forget to update one of the constant definitions? Then this is the tool for you!

Automated design flow

Inventas provides a tool to accelerate and optimize the design flow for handling register interfaces between software and hardware.

Generated output

  • VHDL design files
  • Software header files
  • Testbenches
  • Documentation